esda25b1 ? october 1999 - ed : 2 6 bidirectional transil ? functions very low capacitance : c= 20 pf @ v rm 150 w peak pulse power (8/20 m s) features so-8 functional diagram 1 2 3 4 i/o 1 i/o 2 i/o 3 i/o 4 i/o 6 gnd gnd i/o 5 8 7 6 5 description the esda25b1 is a monolithic voltage suppressor designed to protect components which are connected to data and transmission lines against eds. transil ? array for esd protection application specific discretes a.s.d. ? where transient overvoltage protection in esd sensitive equipment is required, such as : - computer - printers - communication systems it is particulary recommended for rs232 i/o port protection where the line interface withstands only 2 kv esd surges. applications benefits high esd protection level : up to 25 kv high integration suitable for high density boards iec 1000-4-2 : level 4 mil std 883c-method 3015-6 : class 3 (human body model) complies with the following standards : 1/5
symbol parameter v rm stand-off voltage v br breakdown voltage v cl clamping voltage i rm leakage current i pp peak pulse current a t voltage temperature coefficient c capacitance rd dynamic resistance electrical characteristics (t amb = 25c) symbol parameter value unit v pp electrostatic discharge mil std 883c - method 3015-6 25 kv p pp peak pulse power (8/20 m s) 150 w t stg t j storage temperature range maximum junction temperature - 55 to + 150 125 c c t l maximum lead temperature for soldering during 10s 260 c absolute maximum ratings (t amb = 25c) types v br @ i r i rm @ v rm rd a tc min. max. max. typ. max. typ. note 1 note 1 note 2 note 3 0v bias vvma m av w 10 -4 / cpf esda25b1 25 30 1 2 24 1.5 9.7 15 note 1 : between any i/o pin and groung note 2 : square pulse, ipp = 25a, tp=2.5 m s. note 3 : d v br = a t* (tamb -25c) * v br (25c) esda25b1 2/5
the esda family has been designed to clamp fast spikes like esd. generally the pcb designers need to calculate easily the clamping voltage v cl . this is why we give the dynamic resistance in addition to the classical parameters. the voltage across the protection cell can be calculated with the following formula: v cl = v br + rd i pp where ipp is the peak current through the esda cell. dynamic resistance measurement the short duration of the esd has led us to prefer a more adapted test wave, as below defined, to the classical 8/20 m s and 10/1000 m s surges. 2.5 m s duration measurement wave. as the value of the dynamic resistance remains stable for a surge duration lower than 20 m s, the 2.5 m s rectangular surge is well adapted. in addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of rd. calculation of the clamping voltage use of the dynamic resistance 2s tp = 2.5s t i ipp esda25b1 3/5
0 25 50 75 100 125 150 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 ppp[tj initial]/ppp[tj initial=25c] tj initial(c) fig. 1 : peak power dissipation versus initial junction temperature. 20 25 30 35 40 45 50 55 60 0.1 1.0 10.0 50.0 ipp(a) tp=2.5s v (v) cl fig. 3 : clamping voltage versus peak pulse current (tj initial = 25 c). rectangular waveform tp = 2.5 m s. 110100 10 100 1000 2000 ppp(w) tp(s) fig. 2 : peak pulse power versus exponential pulse duration (tj initial = 25 c). 12 510 30 1 2 5 10 20 c(pf) f=1mhz vosc=30mv v (v) r fig. 4 : capacitance versus reverse applied voltage (typical values). 25 50 75 100 125 1 10 100 200 i [tj] / i [tj=25c] rr tj(c) fig. 5 : relative variation of leakage current versus junction temperature (typical values). esda25b1 4/5
package mechanical data so-8 plastic packaging : preferred packaging is tape and reel. weight : 0.08g. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without expres s written ap- proval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - printed in italy - all rights reserved. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com marking : logo, date code, e25b1 ref. dimensions millimeters inches min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.020 c1 45 (typ) d 4.8 5.0 0.189 0.197 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.15 0.157 l 0.4 1.27 0.016 0.050 m 0.6 0.024 s8 (max) order code esda 25 b 1 rl esd array v br min package : so-8 bidirectionel packaging: rl = tape and reel = tube esda25b1 5/5
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